Dr. Peiyi Zhao
Associate Professor
Fowler School of Engineering; Electrical Engineering and Computer Science
Office Location: Keck Center for Science and Engineering Swenson Hall N325
Email: zhao@chapman.edu
- Scholarly Works:
- Digital Commons
- Education:
- Zhejiang University, Bachelor of Science
The University of Louisiana At Lafayette, Ph.D.
Biography
Dr. Zhao's research interests center around the low power consumption of Digital Integrated
Circuits in chip design. Special projects under investigation include flip-flop design,
clock gating design, leakage reduction design, ultra-low power design.
Keywords
low power digital integrated circuits, flip-flop, leakage, clock gating, sub-threshold
Keywords
low power digital integrated circuits, flip-flop, leakage, clock gating, sub-threshold
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Recent Creative, Scholarly Work and Publications
- Zisong Wang, Peiyi Zhao, Tom Springer, Congyi Zhu, Jaccob Mau, Andrew Wells, Yinshui Xia, and Lingli Wang “Low Power Redundant-Transition-Free TSPC Dual-Edge-Triggering Flip-Flop using Single-Transistor-Clocked Buffer”, IEEE Transaction on VLSI, vol. 31, no. 5, pp. 706-710, May 2023
- A. Samiee, P. Borulkar, R. F. DeMara, P. Zhao and Y. Bai, "Low-Energy Acceleration of Binarized Convolutional Neural Networks Using a Spin Hall Effect Based Logic-in-Memory Architecture," in IEEE Transactions on Emerging Topics in Computing, vol. 9, no. 2, pp. 928-940, 1 April 2021